Japanese Patent Laid-open No. 2011-129816 (Patent Literature 1) discloses a conventional memory cell in which a memory gate structure is disposed between two select gate structures (refer to FIG. 15 in Patent Literature 1). The memory cell includes a drain region connected with a bit line and a source region connected with a source line. A first select gate structure, a memory gate structure, and a second select gate structure are disposed in this order on a semiconductor substrate between these drain and source regions. In the memory cell thus configured, a charge storage layer is provided to the memory gate structure. Data is programmed by injecting charge into the charge storage layer, or data is erased by removing charge inside the charge storage layer.
In the case where charge is injected into the charge storage layer in such a memory cell, voltage is blocked by the second select gate structure connected with the source line while a low bit voltage from the bit line is applied to the channel layer of the memory gate structure through the first select gate structure. Simultaneously, a high memory gate voltage is applied to a memory gate electrode in the memory gate structure, and accordingly, charge is injected into the charge storage layer due to the quantum tunneling effect caused by the voltage difference between the bit voltage and the memory gate voltage.